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CPU

The central processing unit (CPU) is the part of a computer that carries out a program's instructions. It repeatedly fetches an instruction from memory, decodes it, executes it and stores the result, all kept in step by a clock ticking billions of times a second. Its instruction set architecture is the contract that lets the same software run on different processor designs.

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ISA versus microarchitecture

The instruction set architecture is the programmer-visible contract: the instruction set, registers, data types, memory architecture (addressing, protection, virtual memory) and input/output handling. A microarchitecture is one implementation of it. Binary compatibility follows the ISA, which is why compilers target an ISA rather than a specific chip.

A simple performance model

tCPU=Ninstr×CPI×1ft_{\text{CPU}} = N_{\text{instr}} \times \text{CPI} \times \dfrac{1}{f}

Execution time = instruction count × average cycles per instruction × cycle time.

Example (our calculation): 2 × 10⁹ instructions at an average CPI of 0.5 on a 3 GHz core take 2 × 10⁹ × 0.5 ÷ (3 × 10⁹) s ≈ 0.33 s. A CPI below 1 is only possible because the core completes more than one instruction per cycle.

  • Pipelining raises throughput; hazards (data dependencies, branches) cause stalls.
  • Branch prediction and out-of-order execution reduce idle cycles.
  • Simultaneous multithreading lets one core manage several instruction streams concurrently.
Common misconception: Comparing clock frequencies across different microarchitectures is misleading: the CPI term can differ by a large factor.
Full explanation — the complete reference version every reading depth is based on

What the CPU does

The CPU performs calculations, executes instructions and moves data between memory, storage and devices such as screens and network adapters. In von Neumann's 1945 description it combines the 'central arithmetic' and 'central control' parts of a computer.

Inside the processor

  • Control unit: interprets each instruction and coordinates the other parts.
  • Arithmetic logic unit (ALU): adds, subtracts, compares and performs logical operations.
  • Registers: a small number of ultra-fast storage locations holding the values in use right now.
  • Cache (L1, L2, L3): fast memory close to the core that keeps frequently used instructions and data.
  • Clock: a timing signal that keeps every operation in step.

The instruction cycle

  1. Fetch: read the next instruction from memory.
  2. Decode: work out what the instruction means and which resources it needs.
  3. Execute: carry out the operation, for example in the ALU.
  4. Store (write back): put the result in a register or in memory, then repeat.
Tcycle=1fT_{\text{cycle}} = \dfrac{1}{f}

The duration of one clock cycle is the reciprocal of the clock frequency f (in hertz, cycles per second).

Worked example

A processor clocked at 3 GHz runs 3 × 10⁹ cycles per second (giga = 10⁹, hertz = per second). One cycle therefore lasts 1 ÷ (3 × 10⁹) s ≈ 3.3 × 10⁻¹⁰ s, about a third of a nanosecond (our calculation). Clock speed alone does not fix how fast a program runs: how much work each cycle completes, and how many cores share the work, matter too.

Instruction set architecture

An instruction set architecture (ISA) defines the instructions, data types, registers, memory access model and input/output handling that software can rely on. Programs are compiled into machine code for a particular ISA; any processor implementing that ISA can run the code, even though different chips build it in very different ways inside.

How we know

The descriptions of the instruction cycle, the parts of a core and the role of the ISA follow Arm's technical glossary (Arm is a company that designs processor architectures). The units — hertz as one per second and giga as 10⁹ — are fixed by the International System of Units.

Assumptions and limits

The four-step cycle is a model. Real cores overlap the steps (pipelining), run instructions out of order and guess which instructions come next (branch prediction), while still producing the results the program expects. Clock frequency also changes as chips speed up or slow down to save energy.

Common misconception: Misconception: 'a higher GHz number always means a faster computer'. Two processors with the same clock frequency can differ greatly in speed, because performance also depends on the design, the number of cores and threads, the caches and the job being done.
Info: Connections: CPUs are built from transistors made of semiconductors, they depend on fast Memory, and they are the 'processing' part of every Computer. Training modern AI models such as transformers leans on parallel processors working alongside the CPU.

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Sources and methodology

  • A CPU (central processing unit) performs calculations, executes program instructions and manages the flow of data between memory, storage and peripheral devices. (awaiting scientific review)
  • A CPU works through a repeating instruction cycle: it fetches the next instruction from memory, decodes it, executes the specified operation, and writes the result back to memory or a register. (awaiting scientific review)
  • Inside a CPU, the control unit directs operation by interpreting instructions, the arithmetic logic unit (ALU) carries out arithmetic and logical operations, and registers are ultra-fast storage locations for the data being worked on. (awaiting scientific review)
  • A CPU's clock generates a timing signal that synchronises the processor's operations. (awaiting scientific review)
  • In the International System of Units the hertz (Hz), the unit of frequency, equals one per second (s⁻¹), and the prefix giga (G) denotes a factor of 10⁹. (awaiting scientific review)
  • An instruction set architecture (ISA) is the interface between a processor's hardware and the software it runs; processors that implement the same ISA can run the same machine code even when their internal designs (microarchitectures) differ. (awaiting scientific review)
  • Multi-core processors place several processing cores on one chip so that tasks can run concurrently, and pipelining overlaps the stages of the instruction cycle to increase throughput. (awaiting scientific review)
  • A higher clock speed does not necessarily mean better performance, because overall performance also depends on the processor's architecture, its core and thread count, its cache design and the workload. (awaiting scientific review)
  • Out-of-order execution reorders instructions to reduce idle time while instructions wait on data dependencies, and branch prediction anticipates which instructions will be needed next to minimise execution delays. (awaiting scientific review)

Claims marked “awaiting scientific review” cite the sources listed but have not yet been signed off by a scientific reviewer.

Content status: published 1 October 2026.

  • Scientific review: this version has not yet been signed off by a scientific reviewer.
  • The Advanced explanation has not yet been reviewed for age suitability.